KADDW/KADDB/KADDQ/KADDD—ADD Two Masks

Opcode/Instruction	Op/En	64/32 bit Mode Support	CPUID Feature Flag	Description
VEX.L1.0F.W0 4A /r KADDW k1, k2, k3	RVR	V/V	AVX512DQ	Add 16 bits masks in k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 4A /r KADDB k1, k2, k3	RVR	V/V	AVX512DQ	Add 8 bits masks in k2 and k3 and place result in k1.
VEX.L1.0F.W1 4A /r KADDQ k1, k2, k3	RVR	V/V	AVX512BW	Add 64 bits masks in k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 4A /r KADDD k1, k2, k3	RVR	V/V	AVX512BW	Add 32 bits masks in k2 and k3 and place result in k1.

Op/En

Operand 1

Operand 2

Operand 3

RVR

ModRM:reg (w)

VEX.1vvv (r)

ModRM:r/m (r, ModRM:[7:6] must be 11b)

Description

Adds the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.

KADDW

DEST[15:0] (cid:197) SRC1[15:0] + SRC2[15:0]
DEST[MAX_KL-1:16] (cid:197) 0

KADDB

DEST[7:0] (cid:197) SRC1[7:0] + SRC2[7:0]
DEST[MAX_KL-1:8] (cid:197) 0

KADDQ

DEST[63:0] (cid:197) SRC1[63:0] + SRC2[63:0]
DEST[MAX_KL-1:64] (cid:197) 0

KADDD

DEST[31:0] (cid:197) SRC1[31:0] + SRC2[31:0]
DEST[MAX_KL-1:32] (cid:197) 0